Q1. Which of the following best describes the difference between computer architecture and computer organization?
A) Architecture deals with hardware implementation, while organization deals with programming languages.
B) Architecture defines programmer-visible attributes, while organization describes their implementation.
C) Architecture deals only with memory, while organization deals only with CPU.
D) Both terms have exactly the same meaning.
Answer: B
Explanation: Computer architecture includes instruction sets, addressing modes and data types. Computer organization deals with implementation details such as control signals, buses and memory technology.
Q2. Which of the following is NOT generally considered a functional unit of a computer?
A) Input unit
B) Memory unit
C) Control unit
D) Compiler
Answer: D
Explanation: A compiler is system software, not a fundamental hardware functional unit.
Q3. In the Von Neumann architecture, instructions and data are stored in:
A) Separate memories
B) The same memory
C) Cache memory only
D) CPU registers only
Answer: B
Explanation: Von Neumann architecture uses a common memory for instructions and data.
Q4. Which limitation is commonly associated with the Von Neumann architecture?
A) Lack of arithmetic operations
B) Von Neumann bottleneck
C) Absence of registers
D) Inability to execute sequential instructions
Answer: B
Explanation: Instructions and data share the same communication path, potentially limiting throughput.
Q5. Which architecture uses separate memories for instructions and data?
A) Von Neumann architecture
B) Harvard architecture
C) Distributed architecture
D) Multiprocessor architecture
Answer: B
Explanation: Harvard architecture has separate instruction and data memories and potentially separate buses.
Q6. Flynn's classification categorizes computer architectures based on:
A) Memory size and CPU speed
B) Number of processors and memory units
C) Instruction and data streams
D) Number of registers
Answer: C
Explanation: Flynn's taxonomy uses instruction streams and data streams to classify SISD, SIMD, MISD and MIMD systems.
Q7. A computer executing one instruction stream on multiple data elements simultaneously is classified as:
A) SISD
B) SIMD
C) MISD
D) MIMD
Answer: B
Explanation: SIMD means Single Instruction Multiple Data and is commonly used in vector processing.
Q8. Which of the following represents an MIMD architecture?
A) A traditional single-core processor
B) A vector processor executing one instruction on multiple data
C) A multiprocessor system executing different instructions on different data
D) A simple calculator
Answer: C
Explanation: MIMD systems allow multiple processors to execute different instruction streams on different data streams.
Q9. The main purpose of the Program Counter (PC) is to:
A) Store the result of arithmetic operations
B) Store the address of the next instruction
C) Store the current instruction permanently
D) Control the ALU
Answer: B
Explanation: The PC normally contains the address of the next instruction to be fetched.
Q10. Which register generally stores the instruction currently being decoded or executed?
A) MAR
B) MDR
C) IR
D) PC
Answer: C
Explanation: The Instruction Register holds the current instruction.
Q11. Which register holds the memory address for a read or write operation?
A) MDR
B) MAR
C) IR
D) Accumulator
Answer: B
Explanation: Memory Address Register (MAR) contains the address of the memory location being accessed.
Q12. Which register temporarily holds data transferred to or from memory?
A) MAR
B) PC
C) MDR
D) IR
Answer: C
Explanation: Memory Data Register (MDR), also called the Memory Buffer Register, holds memory data during transfers.
Q13. A 32-bit processor has an address bus of 32 bits. Assuming byte-addressable memory, the maximum directly addressable space is:
A) 2 GB
B) 4 GB
C) 8 GB
D) 16 GB
Answer: B
Explanation: The number of unique addresses is 2³². With byte addressing, this gives 4 GB.
Q14. Which of the following is generally the fastest storage location?
A) Main memory
B) Cache memory
C) CPU register
D) SSD
Answer: C
Explanation: CPU registers are directly accessible by the processor and are generally faster than cache and main memory.
Q15. The stored-program concept means that:
A) Programs are permanently embedded in hardware
B) Instructions are stored in memory like data
C) Programs cannot be modified
D) Instructions are executed without memory
Answer: B
Explanation: The stored-program concept allows instructions to be stored in memory and fetched by the CPU for execution.
Q16. An instruction generally consists of:
A) Opcode and operand field(s)
B) Only an address field
C) Only a control signal
D) Only an opcode
Answer: A
Explanation: An instruction typically contains an operation code and operand or addressing information.
Q17. Which addressing mode uses the operand value directly within the instruction?
A) Direct addressing
B) Indirect addressing
C) Immediate addressing
D) Indexed addressing
Answer: C
Explanation: In immediate addressing, the actual operand is part of the instruction.
Q18. In direct addressing, the effective address is:
A) Stored in a register
B) Specified directly in the address field
C) Stored in the PC
D) Always equal to zero
Answer: B
Explanation: The address field of the instruction directly specifies the effective memory address.
Q19. In indirect addressing, the address field of the instruction contains:
A) The actual operand
B) The address of the operand's address
C) The opcode
D) The next instruction address
Answer: B
Explanation: The instruction points to a memory location that contains the effective address.
Q20. If an instruction uses indexed addressing, the effective address is generally calculated as:
A) Index register − Address field
B) Index register + Address field
C) PC − Address field
D) MAR + MDR
Answer: B
Explanation: Indexed addressing adds the contents of an index register to the displacement or address field.
Q21. Which addressing mode is commonly used for implementing stack operations?
A) Immediate
B) Stack
C) Direct
D) Implied
Answer: B
Explanation: Stack addressing uses the stack pointer to identify the top of the stack.
Q22. The instruction cycle generally consists of:
A) Fetch, decode and execute
B) Decode, compile and link
C) Input, output and storage
D) Load, save and delete
Answer: A
Explanation: The CPU fetches an instruction, decodes it and executes the required operation. Additional stages may include memory access and write-back.
Q23. During the instruction fetch cycle, the instruction is transferred from memory to:
A) MAR
B) IR
C) ALU
D) Accumulator
Answer: B
Explanation: The fetched instruction is loaded into the Instruction Register.
Q24. Which operation normally increments the Program Counter?
A) Fetching the next sequential instruction
B) Clearing the accumulator
C) Writing data into memory
D) Performing multiplication
Answer: A
Explanation: The PC is updated to point to the next sequential instruction unless a branch or other control-flow operation changes it.
Q25. A microprogrammed control unit generates control signals using:
A) Logic gates only
B) Control memory containing microinstructions
C) Main memory data only
D) External input devices
Answer: B
Explanation: A microprogrammed control unit uses microinstructions stored in control memory to generate control signals.
Q26. Which control unit is generally faster in control-signal generation?
A) Microprogrammed control unit
B) Hardwired control unit
C) Both are always equally fast
D) Software-controlled unit
Answer: B
Explanation: Hardwired control uses fixed logic circuits and can generate control signals without microinstruction fetching overhead.
Q27. The main disadvantage of a hardwired control unit is:
A) Slow execution in every case
B) Difficult modification and design flexibility
C) Requirement of control memory
D) Inability to generate control signals
Answer: B
Explanation: Changing hardwired control logic can be difficult, especially for complex instruction sets.
Q28. A microinstruction is:
A) An instruction executed by an operating system
B) A control word specifying micro-operations
C) A machine instruction stored in cache
D) A program written in assembly language
Answer: B
Explanation: A microinstruction specifies one or more elementary control operations in a microprogrammed control unit.
Q29. Which of the following is a characteristic of RISC architecture?
A) Large number of complex instructions
B) Simple instructions and typically load-store design
C) Variable-length instructions are mandatory
D) Memory-to-memory operations for all arithmetic
Answer: B
Explanation: RISC architectures emphasize simpler instructions, regular formats and register-based operations.
Q30. CISC architecture is generally characterized by:
A) A very small instruction set
B) Complex instructions and multiple addressing modes
C) No memory addressing
D) No control unit
Answer: B
Explanation: CISC designs traditionally provide a larger and more complex instruction set.
Q31. Which instruction changes the normal sequential flow of execution?
A) ADD
B) LOAD
C) Branch
D) STORE
Answer: C
Explanation: Branch instructions modify the PC and redirect program execution.
Q32. In a conditional branch instruction, the branch decision is commonly based on:
A) Cache size
B) Status flags
C) Memory capacity
D) Clock frequency
Answer: B
Explanation: Flags such as Zero, Carry, Sign and Overflow are commonly used to determine whether a conditional branch is taken.
Q33. Which flag indicates that an arithmetic operation produced a zero result?
A) Carry flag
B) Overflow flag
C) Zero flag
D) Sign flag
Answer: C
Explanation: The Zero flag is set when the result of an operation is zero.
Q34. Which flag indicates signed arithmetic overflow?
A) Zero
B) Carry
C) Overflow
D) Parity
Answer: C
Explanation: The Overflow flag indicates that a signed result cannot be represented in the available number of bits.
Q35. The main function of the control unit is to:
A) Perform all arithmetic operations
B) Generate and coordinate control signals
C) Store permanent data
D) Convert analog signals into digital signals
Answer: B
Explanation: The control unit coordinates instruction execution by generating the necessary control signals.
Q36. Which logic gate produces output 1 only when all its inputs are 1?
A) OR
B) NAND
C) AND
D) XOR
Answer: C
Explanation: An AND gate produces 1 only when every input is 1.
Q37. The output of an XOR gate is 1 when:
A) All inputs are 0
B) All inputs are 1
C) An odd number of inputs are 1
D) An even number of inputs are 1
Answer: C
Explanation: XOR produces 1 when the number of asserted inputs is odd.
Q38. Which gate is known as a universal gate?
A) XOR
B) XNOR
C) NAND
D) Buffer
Answer: C
Explanation: NAND alone can be used to implement NOT, AND and OR operations. NOR is also a universal gate.
Q39. According to De Morgan's theorem, the complement of A + B is:
A) A' + B'
B) A'B'
C) AB
D) A + B'
Answer: B
Explanation: (A + B)' = A'B'.
Q40. Simplify the Boolean expression A + AB.
A) AB
B) A
C) B
D) A + B
Answer: B
Explanation: By the absorption law, A + AB = A.
Q41. Simplify A(A + B).
A) A + B
B) AB
C) A
D) B
Answer: C
Explanation: Using the absorption law, A(A + B) = A.
Q42. Which Boolean expression represents the complement of A XOR B?
A) A + B
B) AB
C) A XNOR B
D) A NAND B
Answer: C
Explanation: XNOR is the complement of XOR and produces 1 when both inputs are equal.
Q43. The Boolean expression A + A'B simplifies to:
A) A + B
B) AB
C) A' + B
D) A'B
Answer: A
Explanation: Using the distributive and complement laws, A + A'B = A + B.
Q44. Simplify (A + B)(A + B').
A) A
B) B
C) A + B
D) AB
Answer: A
Explanation: By the distributive law, (A + B)(A + B') = A + BB' = A.
Q45. How many minterms are possible for a Boolean function having five variables?
A) 16
B) 25
C) 32
D) 64
Answer: C
Explanation: A function with n variables has 2ⁿ possible minterms. Therefore, 2⁵ = 32.
Q46. A Boolean function with four variables has how many possible combinations of input values?
A) 8
B) 12
C) 16
D) 32
Answer: C
Explanation: The number of input combinations is 2⁴ = 16.
Q47. Which expression represents the canonical Sum of Products (SOP) form?
A) Product of maxterms
B) Sum of minterms
C) Product of literals only
D) Sum of variables only
Answer: B
Explanation: Canonical SOP is expressed as a sum (OR) of minterms.
Q48. Which expression represents the canonical Product of Sums (POS) form?
A) Sum of minterms
B) Product of maxterms
C) Sum of literals
D) XOR of minterms
Answer: B
Explanation: Canonical POS is expressed as a product (AND) of maxterms.
Q49. The complement of a minterm is:
A) Another minterm
B) A maxterm
C) A don't-care term
D) A prime implicant
Answer: B
Explanation: The complement of a minterm corresponds to the associated maxterm.
Q50. Which of the following is an idempotent law?
A) A + A = A
B) A + A' = 1
C) A × 0 = 0
D) A × 1 = A
Answer: A
Explanation: The idempotent laws are A + A = A and AA = A.
Q51. How many possible Boolean functions can be defined using two variables?
A) 4
B) 8
C) 16
D) 32
Answer: C
Explanation: For n variables, the number of Boolean functions is 2^(2ⁿ). For two variables, this is 2⁴ = 16.
Q52. Which gate is used to detect inequality between two binary inputs?
A) AND
B) OR
C) XOR
D) XNOR
Answer: C
Explanation: XOR produces 1 when its two inputs differ.
Q53. A three-input majority circuit produces output 1 when:
A) All inputs are 0
B) At least two inputs are 1
C) Exactly one input is 1
D) All inputs are different
Answer: B
Explanation: A majority circuit outputs 1 when more than half of its inputs are 1.
Q54. Which binary code is commonly used to represent decimal digits in a weighted form?
A) Gray code
B) Excess-3 code
C) BCD
D) ASCII
Answer: C
Explanation: BCD represents each decimal digit using four binary bits.
Q55. What is the main advantage of Gray code?
A) It minimizes the number of bits
B) Only one bit changes between consecutive code values
C) It supports only decimal numbers
D) It eliminates the need for binary conversion
Answer: B
Explanation: Gray code reduces ambiguity during transitions because adjacent values differ in only one bit.
Q56. A four-variable Karnaugh map contains:
A) 4 cells
B) 8 cells
C) 16 cells
D) 32 cells
Answer: C
Explanation: A K-map for n variables contains 2ⁿ cells.
Q57. In a Karnaugh map, valid group sizes are:
A) Any integer
B) Powers of two
C) Multiples of three
D) Prime numbers only
Answer: B
Explanation: Groups contain 1, 2, 4, 8, 16 and so on adjacent cells.
Q58. A group of eight adjacent cells in a four-variable K-map eliminates how many variables?
A) One
B) Two
C) Three
D) Four
Answer: C
Explanation: A group of 2³ cells eliminates three variables, leaving one variable in the resulting implicant.
Q59. In K-map simplification, don't-care conditions are:
A) Always treated as 1
B) Always treated as 0
C) Used as 0 or 1 when beneficial
D) Never used
Answer: C
Explanation: Don't-care conditions can be assigned either value to obtain simpler expressions.
Q60. A prime implicant is:
A) A group that cannot be combined into a larger valid group
B) Any individual minterm
C) A group containing only zeros
D) A group containing all variables
Answer: A
Explanation: A prime implicant is an implicant that cannot be expanded further by combining adjacent 1-cells.
Q61. An essential prime implicant is one that:
A) Contains every minterm
B) Covers at least one minterm not covered by any other prime implicant
C) Contains only don't-care cells
D) Has the largest number of variables
Answer: B
Explanation: Every essential prime implicant must be included in a minimum cover.
Q62. A half-adder has:
A) Two inputs and one output
B) Two inputs and two outputs
C) Three inputs and two outputs
D) Three inputs and three outputs
Answer: B
Explanation: A half-adder has Sum and Carry outputs.
Q63. The Sum output of a half-adder is:
A) A AND B
B) A OR B
C) A XOR B
D) A XNOR B
Answer: C
Explanation: The Sum output is A XOR B.
Q64. The Carry output of a half-adder is:
A) A + B
B) AB
C) A XOR B
D) A'B
Answer: B
Explanation: Carry is generated only when both inputs are 1.
Q65. A full-adder has:
A) Two inputs and two outputs
B) Three inputs and two outputs
C) Three inputs and three outputs
D) Four inputs and two outputs
Answer: B
Explanation: A full-adder accepts A, B and Carry-in and generates Sum and Carry-out.
Q66. The Sum output of a full-adder is:
A) A + B + Cin
B) A XOR B XOR Cin
C) AB + Cin
D) AB XOR Cin
Answer: B
Explanation: The sum is the XOR of all three input bits.
Q67. How many half-adders are required to implement a full-adder using half-adders and an OR gate?
A) One
B) Two
C) Three
D) Four
Answer: B
Explanation: Two half-adders and one OR gate can implement a full-adder.
Q68. A combinational circuit is one in which the output depends on:
A) Present inputs only
B) Previous inputs only
C) Clock pulses only
D) Stored state only
Answer: A
Explanation: Combinational circuits have no memory; their outputs depend on current inputs.
Q69. A 4-to-1 multiplexer requires how many select lines?
A) 1
B) 2
C) 3
D) 4
Answer: B
Explanation: A multiplexer with 2ⁿ input lines requires n select lines. Therefore, log₂4 = 2.
Q70. A 3-to-8 decoder requires:
A) 2 inputs
B) 3 inputs
C) 8 inputs
D) 11 inputs
Answer: B
Explanation: A 3-to-8 decoder uses three input bits to activate one of eight outputs.
Q71. Which flip-flop is known as a universal flip-flop?
A) SR
B) D
C) JK
D) T
Answer: C
Explanation: A JK flip-flop can perform set, reset, hold and toggle operations.
Q72. What happens in a JK flip-flop when J = 1 and K = 1?
A) Reset
B) Set
C) Toggle
D) Hold
Answer: C
Explanation: When both inputs are 1, the JK flip-flop complements its previous state.
Q73. The race-around condition is associated with:
A) D flip-flop
B) Level-triggered JK flip-flop
C) T flip-flop only
D) SR latch only
Answer: B
Explanation: In a level-triggered JK flip-flop, J = K = 1 and a long clock pulse can cause repeated toggling.
Q74. Which technique can eliminate the race-around condition?
A) Increasing memory size
B) Master-slave configuration
C) Reducing the number of inputs
D) Using an encoder
Answer: B
Explanation: A master-slave JK flip-flop separates sampling and output updates to prevent repeated toggling during one clock pulse.
Q75. A D flip-flop is primarily used for:
A) Storing one bit of information
B) Performing multiplication
C) Generating addresses
D) Encoding decimal values
Answer: A
Explanation: A D flip-flop stores the input bit at the active clock edge.
Q76. The characteristic equation of a D flip-flop is:
A) Q(next) = D
B) Q(next) = Q'
C) Q(next) = JQ' + K'Q
D) Q(next) = T XOR Q
Answer: A
Explanation: The next state of a D flip-flop equals its D input.
Q77. The characteristic equation of a T flip-flop is:
A) Q(next) = T
B) Q(next) = Q XOR T
C) Q(next) = Q + T
D) Q(next) = Q'T
Answer: B
Explanation: When T = 0, the state holds; when T = 1, it toggles.
Q78. Which flip-flop is commonly used in binary counters?
A) D only
B) T
C) SR only
D) None of these
Answer: B
Explanation: T flip-flops are convenient for implementing binary counting circuits.
Q79. An n-bit binary counter can represent how many distinct states?
A) n
B) 2n
C) 2ⁿ
D) n²
Answer: C
Explanation: An n-bit counter has 2ⁿ possible binary states.
Q80. A 4-bit ripple counter has a maximum count of:
A) 8
B) 15
C) 16
D) 32
Answer: B
Explanation: A 4-bit counter counts from 0000 to 1111, representing decimal 0 to 15.
Q81. A 5-bit Johnson counter can have a maximum of how many distinct states?
A) 5
B) 10
C) 16
D) 32
Answer: B
Explanation: An n-bit Johnson counter has 2n distinct states. Therefore, 2 × 5 = 10.
Q82. A ring counter with four flip-flops normally has:
A) 4 states
B) 8 states
C) 16 states
D) 32 states
Answer: A
Explanation: A four-bit one-hot ring counter cycles through four states.
Q83. Which counter has a shorter propagation-delay problem?
A) Asynchronous counter
B) Synchronous counter
C) Ripple counter
D) All have identical delay
Answer: B
Explanation: In synchronous counters, all flip-flops receive a common clock, reducing cumulative ripple delay.
Q84. A shift register is primarily used for:
A) Parallel-to-serial and serial-to-parallel conversion
B) Arithmetic division only
C) Memory address decoding
D) Instruction decoding
Answer: A
Explanation: Shift registers can convert data between serial and parallel formats.
Q85. Which register allows data to be shifted in both directions?
A) SISO
B) SIPO
C) Bidirectional shift register
D) PISO
Answer: C
Explanation: A bidirectional shift register supports both left and right shifting.
Q86. A decoder with n input lines can generate a maximum of:
A) n outputs
B) 2n outputs
C) 2ⁿ outputs
D) n² outputs
Answer: C
Explanation: Each possible n-bit combination corresponds to one of 2ⁿ outputs.
Q87. The main function of an encoder is to:
A) Convert coded inputs into a larger number of outputs
B) Convert one of many active inputs into a coded output
C) Store binary information
D) Perform arithmetic operations
Answer: B
Explanation: An encoder produces a binary code corresponding to the active input.
Q88. A priority encoder resolves the situation when:
A) No input is available
B) Multiple inputs are active simultaneously
C) The clock is disabled
D) The output is analog
Answer: B
Explanation: It assigns priority to inputs and encodes the highest-priority active input.
Q89. A 16-to-1 multiplexer requires how many select lines?
A) 2
B) 3
C) 4
D) 16
Answer: C
Explanation: log₂16 = 4 select lines are required.
Q90. Which circuit performs the reverse operation of a multiplexer?
A) Encoder
B) Decoder
C) Demultiplexer
D) Comparator
Answer: C
Explanation: A demultiplexer routes one input to one of several outputs based on select lines.
Q91. Register Transfer Language (RTL) is used to describe:
A) Software compilation
B) Data transfers and operations among registers
C) Network protocols
D) File system operations
Answer: B
Explanation: RTL represents register transfers and micro-operations at the register-transfer level.
Q92. The RTL statement R2 ← R1 means:
A) Transfer R2 into R1
B) Transfer R1 into R2
C) Exchange R1 and R2
D) Clear both registers
Answer: B
Explanation: The arrow indicates that the contents of R1 are transferred to R2.
Q93. A bus is primarily used to:
A) Perform arithmetic operations
B) Transfer information among computer components
C) Store instructions permanently
D) Decode opcodes
Answer: B
Explanation: A bus provides a shared communication path for transferring data, addresses or control information.
Q94. A common bus system using multiplexers can select data from:
A) Only one register permanently
B) Multiple source registers
C) Only memory locations
D) Only the ALU
Answer: B
Explanation: Multiplexers select one of several register outputs to place on the common bus.
Q95. Which micro-operation shifts all bits of a register one position to the left?
A) Arithmetic right shift
B) Logical right shift
C) Left shift
D) Rotate right
Answer: C
Explanation: A left-shift operation moves each bit one position toward the most significant position.
Q96. A circular shift operation is also called:
A) Arithmetic shift
B) Rotation
C) Logical complement
D) Addition
Answer: B
Explanation: Rotation moves the bit shifted out of one end back into the opposite end.
Q97. Which operation is used to clear a register?
A) R ← R + 1
B) R ← 0
C) R ← R'
D) R ← R − 1
Answer: B
Explanation: Loading zero into all register bits clears the register.
Q98. The micro-operation R ← R + 1 is called:
A) Decrement
B) Increment
C) Complement
D) Shift
Answer: B
Explanation: An increment operation increases the register value by one.
Q99. Which of the following is a logical micro-operation?
A) Addition
B) Subtraction
C) AND
D) Increment
Answer: C
Explanation: AND, OR, XOR and complement are logical micro-operations.
Q100. Which operation is performed by the statement R1 ← R2 AND R3?
A) Arithmetic addition
B) Logical conjunction
C) Arithmetic subtraction
D) Circular shift
Answer: B
Explanation: The AND operation is applied bit by bit to the contents of R2 and R3.
Q101. Which register normally holds the address of the top of the stack?
A) PC
B) SP
C) IR
D) MDR
Answer: B
Explanation: The Stack Pointer (SP) identifies the current top of the stack.
Q102. In a push operation on a descending stack, the stack pointer generally:
A) Increases
B) Decreases
C) Remains unchanged
D) Becomes zero
Answer: B
Explanation: In a descending stack, new entries are placed at lower memory addresses, so the SP decreases. Exact implementation depends on the architecture.
Q103. Which micro-operation transfers information from memory to a register?
A) Memory write
B) Memory read
C) Register complement
D) Logical shift
Answer: B
Explanation: A memory-read operation retrieves data from the addressed memory location.
Q104. Which bus carries the memory location address?
A) Data bus
B) Address bus
C) Control bus
D) Expansion bus only
Answer: B
Explanation: The address bus carries the address of the memory or I/O location being accessed.
Q105. Which bus generally carries read/write and interrupt signals?
A) Data bus
B) Address bus
C) Control bus
D) Memory bus only
Answer: C
Explanation: The control bus carries signals that coordinate operations between system components.
Q106. If a register contains 10110110, its 1's complement is:
A) 01001001
B) 01001010
C) 10110111
D) 11001001
Answer: A
Explanation: Inverting every bit of 10110110 gives 01001001.
Q107. The 2's complement of 00101100 is:
A) 11010011
B) 11010100
C) 00101101
D) 10101100
Answer: B
Explanation: Invert the bits to get 11010011 and add 1, producing 11010100.
Q108. Which micro-operation is used to reverse every bit in a register?
A) Increment
B) Decrement
C) Complement
D) Rotate
Answer: C
Explanation: A complement operation changes each 0 to 1 and each 1 to 0.
Q109. In a register transfer, a control function is commonly represented using:
A) A conditional expression
B) A filename
C) A network address
D) A compiler directive
Answer: A
Explanation: A conditional register transfer takes place only when its specified control condition is true.
Q110. A micro-operation generally operates on:
A) Individual bits or register contents
B) Entire application programs
C) Network packets only
D) Disk partitions
Answer: A
Explanation: Micro-operations are elementary operations performed on data stored in registers.
Q111. Which memory is volatile?
A) ROM
B) RAM
C) Flash memory
D) EEPROM
Answer: B
Explanation: RAM generally loses its stored information when power is removed.
Q112. Which memory uses capacitors to store data?
A) SRAM
B) DRAM
C) ROM
D) PROM
Answer: B
Explanation: DRAM stores bits using capacitors that require periodic refreshing.
Q113. SRAM is generally faster than DRAM because:
A) It uses magnetic storage
B) It does not require periodic refreshing
C) It stores data only in ROM
D) It has no transistors
Answer: B
Explanation: SRAM uses bistable storage cells and does not require the periodic refresh operation needed by DRAM.
Q114. Which memory is commonly used to implement CPU cache?
A) DRAM
B) SRAM
C) Optical memory
D) Magnetic tape
Answer: B
Explanation: SRAM offers low access latency and is commonly used in processor caches.
Q115. The main purpose of cache memory is to:
A) Increase hard disk capacity
B) Reduce average memory access time
C) Replace the CPU
D) Store all application files permanently
Answer: B
Explanation: Cache stores frequently or recently accessed data close to the processor.
Q116. Which principle explains why recently accessed data may be accessed again soon?
A) Spatial locality
B) Temporal locality
C) Sequential consistency
D) Mutual exclusion
Answer: B
Explanation: Temporal locality means recently accessed data or instructions are likely to be accessed again.
Q117. Which principle states that nearby memory locations are likely to be accessed?
A) Temporal locality
B) Spatial locality
C) Data dependency
D) Instruction dependency
Answer: B
Explanation: Spatial locality means that memory locations near a recently accessed location are likely to be accessed.
Q118. A direct-mapped cache allows each memory block to map to:
A) Any cache line
B) Exactly one cache line
C) Two cache lines
D) All cache lines
Answer: B
Explanation: Direct mapping assigns each memory block to a unique cache line determined by its index.
Q119. In a fully associative cache, a memory block can be placed in:
A) Only one specific line
B) Any cache line
C) Only the first cache line
D) Only the last cache line
Answer: B
Explanation: Fully associative mapping allows any memory block to occupy any cache line.
Q120. In set-associative mapping, a memory block can be placed in:
A) Any set and any line
B) A specific set and any line within that set
C) Only one fixed line
D) Only main memory
Answer: B
Explanation: The index identifies the set, while the block can occupy any available line in that set.
Q121. A cache has 64 lines and is 4-way set associative. How many sets does it contain?
A) 8
B) 16
C) 32
D) 256
Answer: B
Explanation: Number of sets = 64 / 4 = 16.
Q122. A cache hit occurs when:
A) Requested data is found in cache
B) Cache is completely empty
C) Data is found only on disk
D) The CPU is switched off
Answer: A
Explanation: A cache hit means that the requested memory block is present in the cache.
Q123. Which replacement policy removes the least recently used block?
A) FIFO
B) LRU
C) Random
D) LFU
Answer: B
Explanation: Least Recently Used replaces the block that has not been accessed for the longest time.
Q124. Which replacement algorithm removes the block that entered the cache earliest?
A) LRU
B) FIFO
C) LFU
D) MRU
Answer: B
Explanation: FIFO replaces the block that has been in the cache for the longest time.
Q125. Which cache write policy updates main memory immediately on every cache write?
A) Write-back
B) Write-through
C) Write-allocate
D) No-write-allocate
Answer: B
Explanation: Write-through updates both cache and main memory for every write.
Q126. In a write-back cache, main memory is generally updated:
A) After every CPU read
B) When a modified cache block is evicted or explicitly written back
C) Before every cache write
D) Never
Answer: B
Explanation: Write-back defers the main-memory update until a modified block is written back.
Q127. The hit ratio of a cache is 0.9. What is its miss ratio?
A) 0.01
B) 0.1
C) 0.9
D) 1.9
Answer: B
Explanation: Miss ratio = 1 − hit ratio = 1 − 0.9 = 0.1.
Q128. A cache has a hit time of 5 ns, a miss rate of 10%, and a miss penalty of 50 ns. Using AMAT = Hit time + Miss rate × Miss penalty, the average access time is:
A) 5 ns
B) 10 ns
C) 15 ns
D) 55 ns
Answer: B
Explanation: AMAT = 5 + (0.1 × 50) = 10 ns.
Q129. Which memory is generally used for firmware storage?
A) SRAM
B) DRAM
C) ROM or Flash memory
D) Cache
Answer: C
Explanation: Non-volatile ROM or Flash memory retains firmware when power is removed.
Q130. A memory has 12 address lines and is byte-addressable. Its capacity is:
A) 1 KB
B) 2 KB
C) 4 KB
D) 8 KB
Answer: C
Explanation: Number of addresses = 2¹² = 4096 bytes = 4 KB.
Q131. A memory chip contains 1024 words, each of 8 bits. Its capacity is:
A) 1 KB
B) 2 KB
C) 4 KB
D) 8 KB
Answer: A
Explanation: 1024 × 8 bits = 8192 bits = 1024 bytes = 1 KB.
Q132. Associative memory is also known as:
A) Sequential access memory
B) Content-addressable memory
C) Read-only memory
D) Virtual memory
Answer: B
Explanation: CAM retrieves information based on content rather than a conventional memory address.
Q133. Which memory access method is used by magnetic tape?
A) Random access
B) Direct access
C) Sequential access
D) Associative access
Answer: C
Explanation: Magnetic tape generally requires sequential traversal to reach a particular record.
Q134. Virtual memory primarily allows:
A) CPU clock frequency to increase
B) Programs to use an address space larger than available physical RAM
C) Cache to become non-volatile
D) Registers to store unlimited data
Answer: B
Explanation: Virtual memory provides an abstraction of a large address space using physical memory and secondary storage.
Q135. A page fault occurs when:
A) The requested page is not currently present in physical memory
B) The CPU executes an arithmetic instruction
C) Cache memory is full
D) The PC contains zero
Answer: A
Explanation: A page fault occurs when a process references a virtual-memory page that is not currently resident in RAM.
Q136. Which page replacement algorithm may exhibit Belady's anomaly?
A) LRU
B) Optimal
C) FIFO
D) Stack algorithm
Answer: C
Explanation: FIFO can produce more page faults when the number of available frames increases.
Q137. Which page replacement algorithm is theoretically optimal?
A) FIFO
B) LRU
C) Optimal
D) Random
Answer: C
Explanation: The optimal algorithm replaces the page whose next use is farthest in the future.
Q138. TLB is used to speed up:
A) Cache replacement
B) Virtual-to-physical address translation
C) Disk scheduling
D) Instruction decoding
Answer: B
Explanation: The Translation Lookaside Buffer caches recent page-table translations.
Q139. If a system has a 32-bit virtual address and a page size of 4 KB, the number of page-offset bits is:
A) 8
B) 10
C) 12
D) 16
Answer: C
Explanation: 4 KB = 2¹² bytes, so 12 bits are required for the page offset.
Q140. Which memory hierarchy order is generally correct from fastest to slowest?
A) Hard disk → RAM → Cache → Registers
B) Registers → Cache → RAM → Secondary storage
C) RAM → Registers → Disk → Cache
D) Cache → Disk → Registers → RAM
Answer: B
Explanation: Registers are generally fastest, followed by cache, main memory and secondary storage.
Q141. Pipelining primarily improves:
A) Instruction latency in every case
B) Instruction throughput
C) Memory capacity
D) Program size
Answer: B
Explanation: Pipelining overlaps instruction execution stages to increase the number of instructions completed per unit time.
Q142. A basic five-stage instruction pipeline commonly contains:
A) Fetch, decode, execute, memory access, write-back
B) Input, output, compile, link, execute
C) Fetch, store, delete, print, halt
D) Decode, encode, sort, search, execute
Answer: A
Explanation: These are the common stages of a simplified RISC pipeline.
Q143. A pipeline hazard is a situation that:
A) Always increases cache size
B) Prevents the next instruction from executing in the expected pipeline cycle
C) Eliminates all dependencies
D) Increases the number of registers
Answer: B
Explanation: Hazards can cause stalls, incorrect execution without handling, or pipeline flushing.
Q144. Which hazard occurs when an instruction depends on the result of an earlier instruction?
A) Structural hazard
B) Data hazard
C) Control hazard
D) Cache replacement hazard
Answer: B
Explanation: A data hazard occurs when instruction dependencies prevent safe overlapping execution.
Q145. Which hazard occurs due to resource conflicts?
A) Data hazard
B) Control hazard
C) Structural hazard
D) Branch prediction hazard
Answer: C
Explanation: A structural hazard occurs when multiple instructions need the same hardware resource simultaneously.
Q146. A control hazard is commonly caused by:
A) Branch instructions
B) Register renaming
C) Cache hits
D) Arithmetic addition
Answer: A
Explanation: Branch instructions can change the next instruction address, making the pipeline's predicted instruction stream uncertain.
Q147. Read After Write (RAW) is also known as:
A) Anti-dependency
B) True dependency
C) Output dependency
D) Structural dependency
Answer: B
Explanation: RAW occurs when an instruction reads a value that an earlier instruction must write.
Q148. Write After Read (WAR) is known as:
A) True dependency
B) Anti-dependency
C) Output dependency
D) Control dependency
Answer: B
Explanation: WAR occurs when a later instruction writes a location before an earlier instruction has read its old value.
Q149. Write After Write (WAW) is known as:
A) Output dependency
B) True dependency
C) Control dependency
D) Anti-dependency
Answer: A
Explanation: WAW occurs when two instructions write to the same destination and their write order must be preserved.
Q150. Which technique is commonly used to reduce RAW pipeline stalls?
A) Register renaming alone
B) Data forwarding
C) Increasing instruction size
D) Disabling the ALU
Answer: B
Explanation: Forwarding sends a result directly to a dependent instruction without waiting for it to be written back to the register file.
Q151. A pipeline has five stages, each requiring one clock cycle. Ignoring pipeline overhead, how many cycles are required to execute 10 instructions?
A) 10
B) 14
C) 15
D) 50
Answer: B
Explanation: For a fully balanced pipeline, cycles = k + n − 1 = 5 + 10 − 1 = 14.
Q152. A non-pipelined processor takes five cycles per instruction. A five-stage pipeline takes one cycle per stage. Ignoring overhead, the ideal speedup for a large number of instructions approaches:
A) 1
B) 2
C) 5
D) 10
Answer: C
Explanation: With balanced stages, ideal asymptotic speedup approaches the number of pipeline stages.
Q153. A pipeline with stage delays of 20 ns, 30 ns, 25 ns and 15 ns has a minimum clock period of:
A) 15 ns
B) 20 ns
C) 25 ns
D) 30 ns
Answer: D
Explanation: The pipeline clock period is limited by the slowest stage, which takes 30 ns, ignoring register overhead.
Q154. The maximum ideal throughput of a pipeline with a clock period of 2 ns is:
A) 2 million instructions/second
B) 50 million instructions/second
C) 500 million instructions/second
D) 2 billion instructions/second
Answer: D
Explanation: One instruction per 2 ns gives 1 / (2 × 10⁻⁹) = 500 million instructions/second. Therefore, the correct option should be C.
Q155. Which technique predicts the outcome of a branch instruction?
A) Cache mapping
B) Branch prediction
C) Memory interleaving
D) Register allocation
Answer: B
Explanation: Branch prediction predicts whether a branch will be taken to reduce control-hazard penalties.
Q156. Arithmetic pipelining is commonly used for:
A) Overlapping arithmetic operations
B) Disk formatting
C) Address translation only
D) Interrupt handling only
Answer: A
Explanation: Arithmetic pipelines divide complex arithmetic operations into stages that can process different data simultaneously.
Q157. In a floating-point addition pipeline, which operation normally comes before significand addition?
A) Result normalization
B) Exponent comparison and alignment
C) Result storage
D) Branch prediction
Answer: B
Explanation: Exponents are compared and the smaller significand is shifted to align the exponents before addition.
Q158. SIMD architecture is especially suitable for:
A) Processing independent elements of a vector
B) Executing only one serial instruction
C) Sequential magnetic tape access
D) Operating system booting only
Answer: A
Explanation: SIMD performs the same operation on multiple data elements.
Q159. Which parallel architecture contains multiple processors with their own instruction streams and data streams?
A) SISD
B) SIMD
C) MISD
D) MIMD
Answer: D
Explanation: MIMD systems execute different instructions on different data.
Q160. According to Amdahl's Law, if 40% of a program is inherently serial, the maximum theoretical speedup with infinitely many processors is:
A) 1.5
B) 2
C) 2.5
D) 4
Answer: C
Explanation: Maximum speedup = 1 / serial fraction = 1 / 0.4 = 2.5.
Q161. In a pipeline, a bubble represents:
A) A completed instruction
B) An empty pipeline stage or idle slot
C) A cache hit
D) A memory address
Answer: B
Explanation: A bubble is an idle pipeline slot introduced by a stall or flush.
Q162. Which pipeline design issue occurs when two instructions need the same memory port simultaneously?
A) Control hazard
B) Data hazard
C) Structural hazard
D) Branch hazard
Answer: C
Explanation: Both instructions compete for the same hardware resource.
Q163. A pipeline is considered fully utilized when:
A) Every stage is processing useful work in each cycle
B) All registers are empty
C) Only one instruction is present
D) The CPU is executing a halt instruction
Answer: A
Explanation: Full utilization means all pipeline stages are occupied with useful operations.
Q164. What is the main purpose of superscalar architecture?
A) Execute multiple instructions per clock cycle
B) Execute only one instruction at a time
C) Reduce main memory capacity
D) Eliminate all branch instructions
Answer: A
Explanation: Superscalar processors can issue and execute multiple instructions in one clock cycle using multiple execution units.
Q165. Out-of-order execution allows a processor to:
A) Execute instructions in a different order when dependencies permit
B) Ignore all data dependencies
C) Eliminate the instruction set
D) Execute only branch instructions
Answer: A
Explanation: Independent instructions can execute while an earlier instruction is waiting, while architectural results are maintained correctly.
Q166. The decimal equivalent of binary 110101 is:
A) 51
B) 52
C) 53
D) 54
Answer: C
Explanation: 32 + 16 + 4 + 1 = 53.
Q167. The 2's complement representation of −18 using 8 bits is:
A) 00010010
B) 11101101
C) 11101110
D) 10010010
Answer: C
Explanation: +18 = 00010010. Invert to 11101101 and add 1 to get 11101110.
Q168. What is the range of an 8-bit signed integer represented using 2's complement?
A) −127 to +127
B) −128 to +127
C) −128 to +128
D) −255 to +255
Answer: B
Explanation: The range is −2⁷ to 2⁷ − 1.
Q169. Which number representation has both positive and negative zero?
A) 2's complement
B) 1's complement
C) Unsigned binary
D) Excess-3
Answer: B
Explanation: In 1's complement, all zeros represent positive zero and all ones represent negative zero.
Q170. Which arithmetic representation simplifies signed binary addition and subtraction?
A) Gray code
B) BCD
C) 2's complement
D) ASCII
Answer: C
Explanation: 2's complement allows signed addition and subtraction to use the same binary adder hardware.
Q171. In 8-bit unsigned arithmetic, the result of 250 + 10 is:
A) 250
B) 255
C) 4
D) 260
Answer: C
Explanation: 250 + 10 = 260. Modulo 256, the stored 8-bit result is 4, with a carry-out.
Q172. Signed overflow occurs in 2's complement addition when:
A) Two numbers of opposite signs are added
B) Two numbers of the same sign produce a result with the opposite sign
C) The result is zero
D) The carry-out is always 1
Answer: B
Explanation: Signed overflow occurs when adding operands with the same sign produces a result with a different sign.
Q173. Which method is used to detect signed overflow in 2's complement addition?
A) XOR of carry into and carry out of the sign bit
B) AND of all input bits
C) OR of all output bits
D) Complement of the LSB
Answer: A
Explanation: Overflow is detected when the carry into the most significant bit differs from the carry out.
Q174. The binary representation of decimal 0.625 is:
A) 0.101
B) 0.110
C) 0.011
D) 0.111
Answer: A
Explanation: 0.625 = 1/2 + 1/8 = 0.101₂.
Q175. Which floating-point standard is widely used in modern computers?
A) ASCII
B) IEEE 754
C) Unicode
D) BCD
Answer: B
Explanation: IEEE 754 specifies standard binary and decimal floating-point formats and arithmetic behavior.
Q176. In IEEE 754 single-precision floating-point representation, the exponent field contains:
A) 7 bits
B) 8 bits
C) 10 bits
D) 11 bits
Answer: B
Explanation: Single precision consists of 1 sign bit, 8 exponent bits and 23 fraction bits.
Q177. The bias used in IEEE 754 single-precision floating-point representation is:
A) 63
B) 127
C) 255
D) 1023
Answer: B
Explanation: The exponent bias for single precision is 127.
Q178. The exponent bias in IEEE 754 double precision is:
A) 127
B) 255
C) 512
D) 1023
Answer: D
Explanation: Double precision uses an 11-bit exponent field with a bias of 1023.
Q179. Which value is represented by an all-ones exponent and a zero fraction in IEEE 754?
A) Zero
B) Infinity
C) Normalized number
D) Subnormal number
Answer: B
Explanation: An all-ones exponent and zero fraction represent positive or negative infinity, depending on the sign bit.
Q180. In IEEE 754, a NaN value indicates:
A) Positive zero
B) Negative zero
C) Not a Number
D) Positive infinity
Answer: C
Explanation: NaN represents an undefined or unrepresentable numerical result.
Q181. Booth's multiplication algorithm is mainly used for:
A) Unsigned division
B) Signed binary multiplication
C) Floating-point normalization
D) Cache replacement
Answer: B
Explanation: Booth's algorithm efficiently performs signed multiplication using 2's complement representation.
Q182. Restoring division algorithm is used for:
A) Binary division
B) Binary multiplication
C) Address decoding
D) Cache mapping
Answer: A
Explanation: Restoring division performs binary division by subtracting the divisor and restoring the partial remainder when necessary.
Q183. Which component performs arithmetic and logical operations in a CPU?
A) Control unit
B) ALU
C) MAR
D) PC
Answer: B
Explanation: The Arithmetic Logic Unit performs arithmetic and logical operations.
Q184. The main function of an accumulator is to:
A) Store intermediate arithmetic and logical results
B) Store memory addresses permanently
C) Generate clock pulses
D) Decode memory instructions
Answer: A
Explanation: An accumulator is a register used to hold intermediate results during arithmetic and logical operations.
Q185. Which operation is equivalent to multiplying an unsigned binary number by 2?
A) Logical right shift by one
B) Logical left shift by one
C) Arithmetic right shift by one
D) Rotate right by one
Answer: B
Explanation: A one-bit left shift multiplies an unsigned binary value by 2, provided overflow is not considered.
Q186. Dividing an unsigned binary number by 2 can generally be performed using:
A) Logical left shift
B) Logical right shift
C) Rotate left
D) Bitwise XOR
Answer: B
Explanation: A one-bit logical right shift performs integer division by 2, discarding any fractional remainder.
Q187. Which technique reduces the number of partial products in binary multiplication?
A) Booth encoding
B) FIFO
C) LRU
D) Gray coding
Answer: A
Explanation: Booth recoding reduces partial products, particularly for sequences of consecutive 1s.
Q188. Carry-lookahead addition improves performance by:
A) Waiting for each carry to ripple through every bit
B) Computing carry signals using generate and propagate logic
C) Eliminating the sum operation
D) Using only serial processing
Answer: B
Explanation: Carry-lookahead logic calculates carries in parallel using generate and propagate terms.
Q189. In a carry-lookahead adder, the generate function for bit i is commonly defined as:
A) Gi = Ai XOR Bi
B) Gi = Ai AND Bi
C) Gi = Ai OR Bi
D) Gi = Ai NAND Bi
Answer: B
Explanation: A carry is generated at bit i when both Ai and Bi are 1.
Q190. In a carry-lookahead adder, the propagate function is commonly defined as:
A) Ai AND Bi
B) Ai XOR Bi
C) Ai NOR Bi
D) Ai NAND Bi
Answer: B
Explanation: Under the XOR propagate convention, a carry-in is propagated when exactly one input bit is 1.
Q191. The main disadvantage of a ripple-carry adder is:
A) Large memory requirement
B) Carry propagation delay
C) Inability to perform addition
D) Requirement of floating-point numbers
Answer: B
Explanation: Each stage must wait for the previous stage's carry, resulting in delay proportional to the number of bits.
Q192. Which architecture uses a stack-based operand organization?
A) Accumulator-based architecture
B) Stack-based architecture
C) General-purpose register architecture
D) Harvard architecture
Answer: B
Explanation: Stack-based architectures use a stack for storing operands and intermediate results.
Q193. Which architecture typically uses instructions with explicit register operands?
A) Stack architecture
B) General-purpose register architecture
C) Pure accumulator architecture
D) Analog architecture
Answer: B
Explanation: General-purpose register architectures use registers to hold operands and results explicitly.
Q194. The main purpose of an interrupt is to:
A) Stop the CPU permanently
B) Notify the CPU that an event requires attention
C) Increase cache capacity
D) Replace the instruction register
Answer: B
Explanation: An interrupt temporarily redirects CPU execution to an interrupt service routine.
Q195. Which interrupt cannot normally be disabled by the processor's ordinary interrupt-disable mechanism?
A) Maskable interrupt
B) Non-maskable interrupt
C) Software interrupt
D) Timer interrupt
Answer: B
Explanation: A non-maskable interrupt is designed for critical events and cannot be disabled through ordinary interrupt masking.
Q196. DMA stands for:
A) Direct Memory Access
B) Dynamic Memory Allocation
C) Data Management Architecture
D) Digital Memory Addressing
Answer: A
Explanation: Direct Memory Access allows devices to transfer data to or from memory with limited CPU involvement.
Q197. Which DMA mode allows a DMA controller to transfer a block of data while temporarily taking control of the system bus?
A) Cycle stealing
B) Burst mode
C) Programmed I/O
D) Interrupt polling
Answer: B
Explanation: In burst mode, the DMA controller transfers a block of data in consecutive bus cycles.
Q198. In programmed I/O, the CPU generally:
A) Never communicates with the I/O device
B) Repeatedly checks the device status or polls it
C) Always uses DMA
D) Transfers data without executing instructions
Answer: B
Explanation: Programmed I/O commonly uses polling, in which the CPU checks the device's status register.
Q199. Which technique allows multiple memory banks to operate in an overlapping manner?
A) Memory interleaving
B) Cache invalidation
C) Branch prediction
D) Register renaming
Answer: A
Explanation: Memory interleaving distributes consecutive memory addresses across multiple banks to improve access bandwidth.
Q200. A computer has a clock frequency of 2 GHz and executes 4 billion instructions in 2 seconds. What is its average CPI?
A) 0.5
B) 1
C) 2
D) 4
Answer: B
Explanation: Total clock cycles = 2 × 10⁹ × 2 = 4 × 10⁹. CPI = Total cycles / Instructions = 4 × 10⁹ / 4 × 10⁹ = 1.